The present invention relates to an internal voltage generating circuit in a semiconductor memory device, and more particularly, to an internal voltage generating circuit for pumping a power supply voltage to generate a high voltage used in a semiconductor memory device, and a method for operating the same.
In a system with a plurality of semiconductor devices, a semiconductor memory device is used as data storage. The semiconductor memory device outputs data corresponding to addresses received from a data processor, e.g., a central processing unit (CPU), or stores data received from the data processor into unit cells corresponding to addresses inputted together with the data.
As the integration density of the semiconductor memory device increases, circuits are designed in accordance with a sub-micron or nano-scale design rule. Components of the memory circuits are extremely scaled down. As the operating frequency of the CPU increases, a semiconductor memory device is designed such that it can operate at a high frequency. To this end, an operating voltage must also be lowered. For example, a power supply voltage of less than 1.5 V is used in a double data rate—version 3 (DDR3) or higher-performance synchronous semiconductor memory device, which are considered as next generation memory devices.
The operating voltage of the next generation semiconductor memory device decreases and different internal voltages are required for supporting a variety of operations within the semiconductor memory device. It is difficult and inefficient to receive the operating voltage and the different internal voltages from the outside. For this reason, an internal voltage generating circuit is separately provided in the semiconductor memory device. The internal voltage generating circuit generates internal voltages according to an external power supply voltage. A voltage level of the internal voltage may be substantially equal to or different from that of the external power supply voltage. For example, the internal voltage may be ½ times, ¼ times or two times the voltage level of the external power supply voltage.
The importance of on-chip high voltage generating circuits is increasing. The high voltage generating circuit generates a high voltage higher than the power supply voltage. The high voltage generating circuit is adopted for driving word lines connected to unit cells in the semiconductor memory device. In addition, the high voltage is used as a driving voltage of a data output buffer.
With the high integration of the semiconductor memory device, the number of banks increases like 4 banks, 8 banks, 16 banks, etc. A frequency of a clock signal increases with an increasing operating speed of the memory device. In spite of the high integration of the semiconductor memory device, the chip size increases with an increasing storage capacity of the semiconductor memory device. In order to maintain a high voltage VPP at a voltage level higher than a predetermined level, a pumping circuit is enabled according to a detected voltage level of a high voltage VPP. However, as the chip size increases, an operation margin for generating the high voltage VPP through the pumping operation is reduced by a delay time taken to transfer the high voltage VPP to the pumping circuit and a high-frequency clock signal. Further, since the size of a capacitor is reduced with an increasing net die, it is difficult to stabilize the voltage level of the high voltage VPP.
FIG. 1 is a block diagram of a conventional semiconductor memory device.
Referring to FIG. 1, the semiconductor memory device includes a high voltage detecting unit 120, an active pumping unit 140, and a standby pumping unit 160. The high voltage detecting unit 120 detects a voltage level of a high voltage VPP and outputs a pumping determining signal VPP_DET of a logic high level for enabling the pumping units when the detected voltage level of the high voltage VPP is below a predetermined level. Also, the high voltage detecting unit 120 outputs a pumping determining signal VPP_DET of a logic low level when the detected voltage level of the high voltage VPP is above the predetermined level. The pumping determining signal VPP_DET is transferred to the active pumping unit 140 and the standby pumping unit 160. The active pumping unit 140 or the standby pumping unit 160 is enabled to generate the high voltage VPP according to an active signal ACTIVE indicating an operation state of the semiconductor memory device. The active signal ACTIVE indicates that a bank of the semiconductor memory device is enabled.
FIG. 2 is a circuit diagram illustrating a controller 142 of the active pumping unit 140 and a controller 162 of the standby pumping unit 160 in FIG. 1.
Referring to FIG. 2, the active pumping unit 140 operates only when the bank is enabled. The active pumping unit 140 includes a first controller 142 for enabling the pumping operation only when both the active signal ACTIVE and the pumping determining signal VPP_DET are activated. Specifically, the active pumping unit 140 performs the pumping operation only when an active pumping enable signal ACTIVE_PUMP_ENABLE outputted from the first controller 142 is activated to a logic high level.
On the other hand, the standby pumping unit 160 performs the pumping operation in response to the pumping determining signal VPP_DET when the voltage level of the high voltage VPP is below the predetermined level, regardless of the enabling of the bank. A second controller 162 of the standby pumping unit 160 buffers the pumping determining signal VPP_DET to output a standby pumping enable signal STANDBY_PUMP_ENABLE. The standby pumping unit 160 may be implemented with two inverters as illustrated in FIG. 2.
FIG. 3 is a timing diagram illustrating an operation of the semiconductor memory device of FIG. 1.
Referring to FIG. 3, the active pumping unit 140 and the standby pumping unit 160 are enabled by the active signal ACTIVE indicating the enabling of the bank and the pumping determining signal VPP_DET indicating that the voltage level of the high voltage VPP is below the predetermined level. When the bank is enabled, the high voltage VPP is used in word lines and various internal circuits of the semiconductor memory device and thus the active pumping unit 140 needs to be enabled.
Upon driving the pumping circuit, if a bank active interval is shortened due to the increase of the operating speed of the semiconductor memory device, the consumption of the high voltage VPP increases suddenly while the bank is enabled. As a result, the active pumping unit 140 may not cope with the sudden consumption of the high voltage VPP. Moreover, as the chip size increases, the time delay occurs in transferring the pumping determining signal VPP_DET to the active pumping units 140 of the chip. As the operating speed of the semiconductor memory device, the time delay cannot be ignored. Due to the time delay, a timing when the pumping circuit is enabled does not coincide with a timing when the consumption of the high voltage VPP. Consequently, the voltage level of the high voltage VPP becomes unstable.